Papers

Export 1 results:
Filters: Keyword is VHDL and Author is Renau, Jose  [Clear All Filters]
2008
S. Sudakrishnan, Madhavan, J., Whitehead, Jr., J. E., and Renau, J., Understanding bug fix patterns in verilog, in Proceedings of the 2008 international working conference on Mining software repositories, New York, NY, USA, 2008, pp. 39–42.PDF icon p39-sudakrishnan.pdf (131.86 KB)