@conference {Sudakrishnan:2008:UBF:1370750.1370761,
	title = {Understanding bug fix patterns in verilog},
	booktitle = {Proceedings of the 2008 international working conference on Mining software repositories},
	series = {MSR {\textquoteright}08},
	year = {2008},
	pages = {39{\textendash}42},
	publisher = {ACM},
	organization = {ACM},
	address = {New York, NY, USA},
	abstract = {Today, many electronic systems are developed using a hardware description language, a kind of software that can be converted into integrated circuits or programmable logic devices. Like traditional software projects, hardware projects have bugs, and significant developer time is spent fixing them. A useful first step toward reducing bugs in hardware is developing an understanding of the frequency of different types of errors. Once the most common types are known, it is then possible to focus attention on eliminating them. As most hardware projects use software configuration management repositories, these can be mined for the textual bug fix changes. In this project, we analyze the bug fix history of four hardware projects written in Verilog and manually define 25 bug fix patterns. The frequency of each bug type is then computed for all projects. We find that 29 -- 55\% of the bug fix pattern instances in Verilog involve assignment statements, while 18 -- 25\% are related to if statements.},
	keywords = {bug fixing, error classification, hdl, verilog, VHDL},
	isbn = {978-1-60558-024-1},
	doi = {http://doi.acm.org/10.1145/1370750.1370761},
	url = {http://doi.acm.org/10.1145/1370750.1370761},
	attachments = {https://flosshub.org/sites/flosshub.org/files/p39-sudakrishnan.pdf},
	author = {Sudakrishnan, Sangeetha and Madhavan, Janaki and Whitehead,Jr., E. James and Renau, Jose}
}
